In present semiconductor technology, Complementary Metal-Oxide Semiconductor (CMOS) devices, such as n-type Metal oxide Semiconductor (MOS) transistors and p-type MOS transistors, are typically fabricated on semiconductor wafers. The semiconductor wafers are typically silicon wafers. Most of today's semiconductor devices are built on silicon substrates having a (100) crystal orientation, which substrates are referred to as (100) substrates.
Electrons are known to have high mobility in silicon substrate having a (100) silicon crystal orientation, and holes are known to have high mobility in silicon substrate having a (110) crystal orientation. Typically, the electron mobility in a (100) silicon substrate is roughly two times to about four times higher than the hole mobility values in the same substrate. On the other hand, the hole mobility in a (110) silicon substrate is about two times higher than that in a (100) silicon substrate. Therefore, the p-type MOS transistors formed on a (110) surface will exhibit significantly higher drive currents than the p-type MOS transistors formed on a (100) surface. Unfortunately, the electron mobility on (110) surfaces are significantly degraded compared to that on (100) surfaces.
In addition, p-type MOS transistors and n-type MOS transistors have different preferences regarding the strains. The performance of a MOS transistor can be enhanced through a stressed-surface channel. This technique allows the performance of a MOS transistor to be improved at a constant gate length, without adding complexity to circuit fabrication or design. Research has revealed that a tensile stress in the channel-length direction can improve the performance of n-type MOS transistors, and a compressive stress in channel length-direction can improve the performance of p-type MOS transistors.